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High-speed Interconnect IP Portfolio

Qualitas Semiconductor delivers a comprehensive lineup of high-speed,
silicon-proven interface IPs, enabling customers to build reliable,
power-efficient, and high-performance SoCs.

Our IPs are optimized for next-generation applications across AI, HPC, automotive, mobile, and edge devices.
Built on advanced process nodes and designed with area-efficient architectures, our IPs help customers maximize integration flexibility while minimizing power and footprint.

100G SERDES PAM4 PHY

Elevating High-Speed Connectivity with
Precision and Power Efficiency

Qualitas Semiconductor’s SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps. It supports diverse applications including AI accelerators, data centers, 5G infrastructure, and automotive SoCs.

The Ethernet PHY IP is optimized for CEI-112G and supports 8b/10b encoding for Gen1/Gen2 and 128b/130b for Gen3/Gen4, ensuring accurate serialization and deserialization of data streams.

With robust equalization and proven interoperability, it maintains high signal integrity across lossy channels and is well-suited for advanced SoC integration.

100G SERDES PAM4 PHY

Block Diagram

Features

  • Transmit Path:

    Accepts four 10-bit transmit characters (8b/10b) or four 8-bit data blocks (128b/130b)

    Serializes data to differential outputs (TXP/TXN) at up to 16.0Gb/s per lane

  • Receive Path:

    Samples incoming serial data from differential inputs (RXP/RXN)

    Deserializes into four 10-bit (8b/10b) or 8-bit (128b/130b) received characters

  • Optimized for high-speed Ethernet, PCIe, and custom protocol applications
  • Integrated with robust equalization and low-jitter clock recovery for enhanced signal integrity

20G MSS(Multi-standard SERDES) PHY

Block Diagram

Features

  • Developing under SF4X CMOS technology (2025.06.30 MTO)
  • Compliant to multiple standards, max datarate 20Gb/s
  • Channel Configuration for Data Lanes: 1, 2 or 4 Data Lanes
  • Reliable Ring OSC PLL based architecture for Low power consumption
  • 3-tap TX FFE, RX CTLEs and 5-tap DFE w/ channel adaptation
  • Support built in Eye Open Monitor (EOM) and Built In Self Test(BIST)

PCI Express® (PCIe) PHY IP Solutions

The Key Interface IP Essential
For Use In the Era of Artificial Intelligence

Qualitas Semiconductor’s PCIe PHY IP supports PCIe Gen 4.0, 5.0, and 6.0, and is validated through interoperability testing in collaboration with global partners,
ensuring a production-ready and reliable solution.

It offers a cost-effective, low-power, and area-efficient solution built on advanced FinFET CMOS technology, making it suitable for high-performance and
power-sensitive designs. The IP includes all necessary ESD I/Os and bump pads, and supports robust built-in self-test (BIST) features such as loopback and
scan test, enhancing both reliability and debug efficiency.

PCIe Gen5/6

Qualitas Semiconductor’s PCIe PHY IP supports PCIe Gen 4.0, 5.0, and 6.0, and is validated through interoperability testing in collaboration with global partners,


Built on advanced FinFET process nodes, the IPs incorporate DSP-based equalization, low latency, and industry-proven interoperability—making them ideal for PCIe 6.0 and CXL-ready systems.

Block Diagram

Features

  • Best-in-class Power / Performance / Area competitiveness
  • Compliant to PCIe 5.0/6.x Base specification
  • Supports lane configurations according to the customer’s demands
  • Supports data rates of 2.5GT/s, 5.0GT/s, 8.0GT/s, 16GT/s, 32GT/s and 64GT/s (PAM4)
  • Supports power-down modes of P0, P1, P2, P1.ss and P1.cpm
  • Supports fully adaptive channel equalization
  • Built-in self-test feature producing and checking PRBS random pattern

PCIe Gen4

Qualitas Semiconductor’s PCIe Gen4.0 PHY IP offers a low-power, compact solution with proven performance and robust signal and power integrity, making it suitable for a wide range of high-speed interface environments. Optimized for seamless integration with controller IPs, it enhances design efficiency and reliability. Built-in self-test (BIST), loopback, and scan test features significantly improve debug capability, while optional delivery as a complete PCIe 4.0 subsystem meets diverse customer needs. This robust IP has been successfully deployed in mass-production for applications including data centers, automotive systems, and surveillance devices.

Block Diagram

Features

  • Best-in-class Power / Performance / Area competitiveness
  • Compliant to PCIe 4.0 Base specification
  • Supports lane configurations according to the user’s demands
  • Supports data rates of 2.5GT/s, 5.0GT/s, 8.0GT/s and 16GT/s
  • Including PCS supported in soft-macro form
  • Supports power-down modes of P0, P1, P2, P1.ss and P1.cpm
  • Supports fully adaptive channel equalization
  • Built-in self-test feature producing and checking PRBS pattern

UCIe PHY (Die-to-Die)

A Critical Link Essential
For the Era of Advanced Chiplet Integration

Qualitas Semiconductor’s UCIe PHY IP enables high-bandwidth, low-latency die-to-die communication across chiplets,
fully compliant with the Universal Chiplet Interconnect Express™ (UCIe™) version 2.0 standard.

It supports both Standard and Advanced package types, offering the flexibility needed to build scalable, heterogeneous systems.
Designed for AI accelerators, data center SoCs, and custom multi-die architectures, this PHY IP delivers robust signal integrity and integration-ready support for next-generation chiplet-
based designs.

UCIe PHY (Die-to-Die)

Block Diagram

Features

  • Compliant with UCIe v2.0, supporting 4/8/12/16/24/32GT/s data rates
  • for Standard Package up to 16 lanes / for Advanced Package up to 64 lanes
  • Provides a 1024-bit data bus width with high-throughput die-to-die communication
  • Includes automatic per-lane calibration and optional transmitter de-emphasis
  • Built-in Eye-Opening Monitor (EOM) and loopback test support for both internal and external testing
  • Supports subsystem optimization based on the customer’s chiplet architecture
  • Provides D2D-to-D2D SI/PI modeling and analysis, including full package and board considerations for customer-specific implementations

MIPI PHY & Controller

Enhanced Data Transmission with
State-of-the-Art MIPI Solutions

Qualitas Semiconductor’s MIPI D/C-PHY Combo IP is a mass-proven solution supporting both MIPI D-PHY v3.0 and C-PHY v2.1 standards. The IP is available with our own optional CSI-2 Receiver and DSI-2 Transmitter/Receiver controller IPs, delivering a tightly integrated PHY + Controller package that simplifies system design and accelerates product development.

C/D-PHY

Qualitas Semiconductor’s C/D-PHY Combo IP delivers top-tier PPA characteristics and is mass production-proven across multiple customer SoCs.

It is available as a complete subsystem with Qualitas’ own CSI-2 and DSI-2 controller IPs, enabling streamlined integration for camera and display applications.

The IP can be customized to meet specific SoC requirements, providing design flexibility for diverse system needs.

Block Diagram

Features

C-PHY/D-PHY Combo TX/RX
  • Compliant to MIPI D-PHY v3.0, C-PHY v2.1 specification

    D-PHY TX/RX : 80Mb/s ~ 9.0Gb/s

    C-PHY TX/RX : 80Ms/s ~ 8.0Gs/s

  • Area efficient macro optimized for placement for dense SoC designs
  • Support Uni-(TX or RX) and Bi-directional(TX and RX) mode
  • Support emphasis architecture over lossy channel for TX
  • Support equalize architecture over lossy channel for RX
  • Controllable Bandwidth-power scaling
  • Low power mode turn-on based on channel condition
  • Power gating architecture reduce leakage power
  • Clock gating for low-power consumption
  • Support Eye open monitor
  • Support internal and external loopback test

CSI-2 RX

CSI-2 RX IP supports both C-PHY v1.2 and D-PHY v2.0 interfaces, enabling flexible integration across a wide range of image sensor applications. With built-in link layer capabilities including error detection, lane merging, and pixel format support, this IP ensures reliable and efficient data capture in advanced camera systems. It also supports CSE v2.0, MIPI’s functional safety standard, enhancing system-level reliability for safety-critical applications.

Block Diagram

Features

Standards Compliance
  • MIPI CSI-2 v2.0
  • MIPI C-PHY v1.2 and D-PHY v2.0
  • MIPI CSE v2.0
Link Layer Features
  • Lane merging, virtual channel detection, and programmable data extraction
  • Error detection and correction, including packet-level and protocol decoding errors
  • Supports all pixel formats defined in the CSI-2 standard

DSI-2 TX/RX

DSI-2 TX/RX IP supports both transmit and receive functions in line with the DSI-2 v1.1 and D-PHY v2.0 standards. Designed for modern SoCs integrating display functionality, it supports high-speed and low-power modes, lane configurability, and robust link features—making it ideal for advanced embedded display applications.

Block Diagram

Features

Standards Compliance
  • MIPI DSI-2 v1.1
  • MIPI D-PHY v2.0
Link Layer Features
  • Configurable EoTp
  • Multiple packets per transmission
  • Lane distribution with ECC/CRC error handling
  • Detects all packet-level and protocol decoding errors
  • Supports all pixel formats defined by the standard

Display PHY IP

From Concept to Screen :
Building Future-Ready Display Systems

Qualitas Semiconductor’s Display IP portfolio offers high-performance, low-power solutions for both external and internal display interfaces.Qualitas Semiconductor’s Display IP portfolio offers high-performance, low-power solutions for both external and internal display interfaces.

It includes TX/RX PHY IPs for DisplayPort (DP) and Embedded DisplayPort (eDP), Intra-panel TX PHY IP, and Display Stream Compression (DSC) Encoder and Decoder IPs to support efficient high-resolution data transmission. All IPs are designed with global top-tier PPA efficiency, verified through mass production across customer SoCs, and validated for robust signal and power integrity in both on-chip and off-chip environments.

DP & eDP TX/RX

Qualitas Semiconductor’s DP and eDP TX/RX PHY IP provides a compact, low-power solution for high-speed external display interfaces. It supports various lane configurations, bidirectional data flow in both NS and EW directions, and is optimized for area efficiency on advanced FinFET nodes.

The IP includes built-in self-test features such as loopback mode and PRBS pattern checking, ensuring reliable performance and simplified validation in DisplayPort and Embedded DisplayPort applications.

Block Diagram

Features

  • eDP v1.5 compliant
  • Supports for 1.62Gbps to Max 8.1Gbps data rate
  • PSR, PSR2 supported for low power consumption ( FW_SLEEP, FW_STANDBY supported )
  • Supports for eDP v1.5 feature such as AUX-less Link Training
  • Adaptive continuous time linear equalizer (CTLE) and decision feedback equalization (DFE)
  • Automatic calibration of analog circuits and offset correction
  • Built-in eye open monitor
  • Built-in self-test (BIST) including PRBS7 and eDP Compliant TPS1 to TPS4 generation and checker

Intra-panel TX

Qualitas Semiconductor’s Intra-panel TX PHY IP is a low-power transmitter designed for COG (Chip-on-Glass) and COF (Chip-on-Film) display modules. It supports data rates up to 4.0Gbps, utilizing a DC-coupled differential pair and a push-pull current mode driver with 600mV swing and 6dB pre-emphasis, enabling high-speed and reliable panel-to-display communication.

Block Diagram

Features

Standards Compliance
  • Compliant to multi-protocol interface
  • COG and COF transmitter
  • Data Rate : 120Mbps ~ 4.0Gbps
  • Supports Power Down Mode
  • Supports Low Power Mode during V-blank period
  • Programmable differential transmitter output impedance (75Ω - 180Ω)
  • Pre-emphasis : max 6dB
  • Programmable Byte clock: 1/12
  • HBM 2kV, CDM +/- 500V
  • Supports APB v3.0 Interface
  • Supports SPI interface for DFT purpose

DSC Decoder/Encoder

Qualitas Semiconductor’s DSC Decoder and Encoder IPs support visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.

Block Diagram

Features

  • Compliant with VESA DSC 1.2b, backward compatible with DSC 1.1
  • Supports all mandatory and optional coding schemes:
  • Modified Median-Adaptive Prediction (MMAP)
  • Midpoint Prediction (MPP)
  • Block Prediction (BP)
  • Indexed Color History (ICH)
  • Compatible with MIPI DSI-2 v1.1, DisplayPort 1.4, and HDMI 2.1
  • Real-time, visually lossless encoding and decoding for high-bandwidth displays
  • Configurable maximum resolution and up to 4 slices per line
  • Operates within a single clock domain to avoid CDC (Clock Domain Crossing) issues
  • Supports 8 / 10 / 12-bit per video component
  • Color formats: YCbCr 4:4:4, 4:2:2, 4:2:0 and RGB 4:4:4
  • Processing performance:
  • 3 pixels/clock for 4:4:4
  • 6 pixels/clock for 4:2:2 and 4:2:0

Ethernet PHY IP

Ethernet PHY IP for High-Performance Connectivity

Qualitas Semiconductor’s 56G/64G PAM4 SERDES hard macro IP delivers a high-performance, low-power solution for high-speed serial interfaces. Supporting data rates up to 64Gbps per lane, it is optimized for next-generation Ethernet, PCIe, and custom high-speed links in AI accelerators, networking switches, and chiplet-based SoCs.With support for PAM4 and NRZ signaling, advanced equalization, and scalable lane architecture, this IP ensures robust signal integrity across long-reach and high-loss channels.

Ethernet PHY IP

Block Diagram

Features

  • Compliant to 802.3 Ethernet specification - 200GBASE-KR4, 200GBASE-CR4, 100GBASE-KR4, 100GBASE-CR4, 100GBASE-KR2, 100GBASE-CR2, 50GBASE-KR, 50GBASE-CR, 40GBASE-KR4, 40GBASE-CR4, 25GBASE-KR, 25GBASE-CR, 10GBASE-KR, 10GBASE-CR
  • Data rate supported - Ethernet: NRZ 3.125 - 26.5625Gb/s, PAM4 53.125Gb/s
  • DSP-based architecture using high-performance ADC/DAC for RX/TX
  • Lane configurations: X1, X2 or X4
  • PCS in soft-macro and PMA in hard-macro
  • Reed / Solomon Forward Error Correction(RS FEC)
  • MCU and firmware-driven Link Training(LT)/Auto Negotiation(AN) delivers flexible functionality and tuning.
  • RX eye-opening monitor
  • Loopback feature capable of generating and checking PRBS patterns

SLVS-EC RX PHY IP

High-Speed, Low-Power PHY for
Advanced Imaging Applications

Qualitas Semiconductor’s SLVS-EC RX PHY IP is a high-speed, low-power receiver macro compliant with SLVS-EC v3.0 specification, enabling reliable parallel high-speed data capture from advanced image sensors. The IP supports both synchronous and asynchronous clocking, delivering flexible timing integration for diverse system architectures.

Optimized for applications requiring wide-lane, high-throughput parallel interfaces—such as machine vision, industrial cameras, and high-resolution imaging—this IP supports up to 10 Gbps per lane with a 40-bit parallel data bus and up to x24 lane configurations, providing scalable bandwidth options.

SLVS-EC RX PHY IP

Features

  • Fully compliant with SLVS-EC v3.0 specification.
  • Supports both synchronous and asynchronous clocking.
  • Up to 10Gbps per lane with 40-bit parallel data bus.
  • Maximum output clock frequency of 250MHz.
  • Configurable 20-bit or 40-bit parallel data interface.
  • Lane configurations: x8, x16, x24.
  • North / South lane direction supported for layout flexibility.
  • Low-power, area-efficient mixed-signal architecture.
  • Integrated (RX) CTLEs and 5-tap DFE for adaptive channel equalization.
  • Ring-OSC PLL based architecture for low power operation.
  • Built-in Eye-Opening Monitor (EOM) and Built-In Self-Test (BIST) support.

USB Super-speed+ PHY

Seamless 20Gbps Connectivity
for High-Speed USB Applications

Qualitas Semiconductor’s USB Super-Speed+ PHY IP is a compact and power-efficient interface solution that fully supports the USB 3.2 Gen1 and Gen2 specifications, enabling data rates of 5Gbps, 10Gbps, and up to 20Gbps (Gen2x2). Compliant with PIPE interface standards and featuring support for both host and device modes, this PHY is ideal for SoCs targeting high-speed USB connectivity in mobile, consumer, and computing applications.

Designed with a low-power mixed-signal architecture and robust signal adaptation, the IP ensures reliable performance over varying channels while minimizing area and energy consumption. It supports full-duplex operation, built-in test features, and advanced signal monitoring for streamlined debugging and integration.

USB Super-speed+ PHY

Features

  • Fully compliant with USB 3.2 Gen2 specification.
  • Supports data rates of 5Gbps (Gen1), 10Gbps (Gen2), and 20Gbps (Gen2x2).
  • Compatible with PIPE interface:
  • 8/16/32-bit at original PIPE.
  • 10/20/40/80-bit at SERDES PIPE.
  • Supports both Host and Device operation modes.
  • Full-duplex lane configuration of x1 and x2.
  • North / South lane direction supported for layout flexibility.
  • Low-power, area-efficient mixed-signal architecture.
  • Integrated TX 3-tap FFE and RX CTLEs with 5-tap DFE for adaptive equalization.
  • Ring-OSC PLL based design for low power consumption.
  • Supports LFPS (Low Frequency Periodic Signaling) generation and detection.
  • Supports TX detect RX function in USB3.x mode.
  • Built-in Eye-Opening Monitor (EOM) and Built-In Self-Test (BIST).